Magnetic Random Access Memory (MRAM) is a non-volatile computer memory technology based on magnetoresistance. MRAM differs from volatile Random Access Memory (RAM) in several respects. Because MRAM is non-volatile, MRAM can maintain memory content when the memory device is not powered. Though conventional non-volatile RAM is typically slower than volatile RAM, MRAM has read and write response times that are comparable to that of volatile RAM. Unlike typical RAM technologies that store data as electric charges, MRAM data is stored by magnetoresistive elements. Generally, the magnetoresistive elements are made from two magnetic layers, each of which holds a magnetic orientation. The magnetization of one layer (the “pinned layer”) is fixed in its magnetic orientation, and the magnetization of the other layer (the “free layer”) can be changed by an external magnetic field generated by a programming current. The pinned and free layers are separated by a tunnel barrier layer. The magnetic field of the programming current can cause the magnetic orientations of the two magnetic layers to be either parallel, giving a lower electrical resistance across the layers (“0” state), or antiparallel, giving a higher electrical resistance across the layers (“1” state). The switching of the magnetic orientation of the free layer and the resulting high or low resistance states across the magnetic layers provide for the write and read operations of the typical MRAM cell.
The size of components in integrated circuits is becoming smaller and smaller over time. MRAM cells are relatively small, and the size of the MRAM cell will most likely be further reduced in the future. For example, the top layer may be about 40 nanometers (nm) thick or less in some embodiments. The pinned layer, the free layer, and/or the tunnel barrier layer include sub-layers in many embodiments, so the sub-layers are even smaller. The formation of the electrical connection to the top of the MRAM cell includes forming a dielectric layer over the MRAM cell, smoothing the surface of that dielectric layer with chemical mechanical planarization (CMP), etching a via through the dielectric layer, and then forming a conductive “interconnect” within the open via. The process variation in the CMP and etching process is more than the 40 nm size of the top layer in some embodiments. As a result, the interconnect extending to the top layer of the MRAM cell is not long enough in some cases such that a portion of the dielectric remains between the interconnect and the MRAM cell and the circuit is permanently blocked open. In other instances, the interconnect is too long and passes through the top layer of the MRAM cell so the MRAM cell is permanently shorted.
Accordingly, it is desirable to provide integrated circuits and methods of producing such integrated circuits with MRAM cells and interconnects where the interconnect reliably forms an electrical connection with the MRAM cell without shorting the MRAM cell. In addition, it is desirable to provide integrated circuits and methods of producing integrated circuits that include a higher percentage of properly function MRAM cells (i.e. MRAM cells that are not permanently open or shorted), compared to traditional integrated circuits with MRAM cells. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.